Active reset circuit for reset spread reduction in single-slope adc

ABSTRACT

An image sensor comprises a pixel circuit including a reset transistor and configured to output a pixel signal; and a differential comparator including a pixel input, a reference input, and a comparator output, wherein one of a source or a drain of the reset transistor is connected to the comparator output. In this manner, an active reset method may be incorporated in the image sensor.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a Continuation of application Ser. No.15/198,817, filed Jun. 30, 2016, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

This application relates generally to image sensors. More specifically,this application relates to reduction of reset spread in image sensors.

2. Description of Related Art

Image sensing devices typically consist of an image sensor, generally anarray of pixel circuits, as well as signal processing circuitry and anyassociated control or timing circuitry. Within the image sensor itself,charge is collected in a photoelectric conversion device of the pixelcircuit as a result of the impingement of light. Modern image sensorstypically include tens of millions of pixels (“megapixels” or “MP”).

The accumulated charge is then converted to a digital value. Such aconversion typically requires several circuit components such assample-and-hold (S/H) circuits, analog-to-digital converters (ADCs), andtiming and control circuits, with each circuit component serving apurpose in the conversion. For example, the purpose of the S/H circuitmay be to sample the analog signals from different time phases of thephotoelectric conversion device operation, after which the analogsignals may be converted to digital form by the ADC. To effectivelyconvert the analog signal to digital form in an array having a largenumber of pixel circuits, a collection of ADCs work in parallel, with asingle ADC being shared by many pixels. The particular sharingarrangement depends on the architecture of the image sensor. Forexample, the arrangement may be a column-based arrangement whereby allpixel circuits in a column of the array share a single ADC, ashared-column arrangement whereby several columns of pixel circuitsshare a single ADC, a block-based arrangement whereby a rectangularblock of pixel circuits share a single ADC, and the like.

To reduce noise in an image sensor, a correlated double sampling (CDS)method is often used. In CDS, each pixel circuit in the image sensor issampled twice. In the first measurement, the pixel circuits are resetand the reset voltages from the pixel circuits are measured. This isreferred to as the reset or “P-phase” signal. After the firstmeasurement, the pixel circuits are exposed to light such that thephotoelectric conversion devices collect charge in accordance with thelevel of incident light. These charges are measured in a secondmeasurement, which gives an analog signal equal to the light-exposedvalue plus the reset value. This is referred to as the data or “D-phase”signal. The difference between the two measurements corresponds to thelight-exposed signal for the pixel circuit.

However, for the CDS method to work effectively, it is helpful tominimize variations in the reset signal. In a practical CMOS imagesensor circuit the total variation of the reset values of all of thepixels in the image sensor must be accommodated by both gain amplifierand ADC functions, especially when operating the sensor under a highanalog gain.

For example, in a case where the ADC has an input voltage range of 1 Vand the variation of the reset voltage signal is 100 mV, the voltagerange allocated for the photodiode signal is 900 mV as the ADC mustreproduce the data signal which includes both reset and photodiodevariations. As the gain of the amplifier is increased, both resetvoltage and data voltage values are amplified such that a gain of 8× (or18 dB) results in a voltage variation of the reset signal at the ADCinput of 800 mV, thus leaving only 200 mV for the photodiode signalvariation. In this example, however, a gain level such as 16× (24 dB) isnot possible as there would be no allowance for the reset plusphotodiode signal variation within the allowed ADC input voltage range.

This allowable photodiode signal range is called the “dynamic range” andis an important parameter in image sensor design. To achieve higherdynamic range at any gain level and to increase the maximum usabledynamic range for the image sensor, there exists a need to reduce thereset signal variation in ADC circuits.

BRIEF SUMMARY OF THE INVENTION

Various aspects of the present disclosure relate to an image sensor thatcan implement an active reset method with a single-slope ADC.

In one aspect of the present disclosure, an image sensor comprises apixel circuit including a reset transistor and configured to output apixel signal; and a differential comparator including a pixel input, areference input, and a comparator output, wherein one of a source or adrain of the reset transistor is connected to the comparator output.

In another aspect of the present disclosure, an image processing methodcomprises outputting a pixel signal from a pixel circuit including areset transistor; and outputting a difference signal from a differentialcomparator including a pixel input, a reference input, and a comparatoroutput, wherein one of a source or a drain of the reset transistor isconnected to the comparator output.

In the above aspects of the present disclosure, a digital-to-analogconverter configured to output a reference signal having a ramp waveformis also provided. The digital-to-analog converter may be configured toinitialize to an initial signal level and then output the ramp waveform,at which point the differential comparator is configured to perform aP-phase measurement corresponding to a reset level of the pixel circuit,and the digital-to-analog converter may be configured to subsequentlyre-initialize to the initial signal level and then output the rampwaveform, at which point the differential comparator is configured toperform a D-phase measurement corresponding to a data level of the pixelcircuit.

This disclosure can be embodied in various forms, including hardware orcircuits controlled by computer-implemented methods, computer programproducts, computer systems and networks, user interfaces, andapplication programming interfaces; as well as hardware-implementedmethods, signal processing circuits, image sensor circuits, applicationspecific integrated circuits, field programmable gate arrays, and thelike. The foregoing summary is intended solely to give a general idea ofvarious aspects of the present disclosure, and does not limit the scopeof the disclosure in any way.

DESCRIPTION OF THE DRAWINGS

These and other more detailed and specific features of variousembodiments are more fully disclosed in the following description,reference being had to the accompanying drawings, in which:

FIG. 1 illustrates an exemplary image sensor according to variousaspects of the present disclosure.

FIG. 2A illustrates an exemplary pixel circuit according to variousaspects of the present disclosure.

FIG. 2B illustrates another exemplary pixel circuit according to variousaspects of the present disclosure.

FIG. 3 illustrates another exemplary pixel circuit according to variousaspects of the present disclosure.

FIG. 4A illustrates an exemplary processing chain in an image sensoraccording to various aspects of the present disclosure with analog CDSoperation.

FIG. 4B illustrates an exemplary processing chain in an image sensoraccording to various aspects of the present disclosure with digital CDSoperation.

FIG. 5 illustrates an exemplary pixel circuit with a matched comparatorcircuit according to various aspects of the present disclosure.

FIG. 6 illustrates an exemplary pixel circuit with a single-slope ADCaccording to various aspects of the present disclosure.

FIG. 7A illustrates an exemplary signal waveform diagram of theexemplary pixel circuit according to FIG. 6.

FIG. 7B illustrates an exemplary signal waveform diagram of theexemplary pixel circuit according to FIG. 6 including signal drift.

FIG. 8 illustrates an exemplary active reset circuit for a single-slopeADC according to various aspects of the present disclosure.

FIG. 9 illustrates an exemplary signal waveform diagram of the exemplaryactive reset circuit according to FIG. 8.

DETAILED DESCRIPTION

In the following description, numerous details are set forth, such asflowcharts, data tables, and system configurations. It will be readilyapparent to one skilled in the art that these specific details aremerely exemplary and not intended to limit the scope of thisapplication.

Moreover, while the present disclosure focuses mainly on examples inwhich the ADC circuits are used in image sensors, it will be understoodthat this is merely one example of an implementation. It will further beunderstood that the disclosed S/H circuits can be used in any device inwhich there is a need to convert a signal from analog to digital and/orcompare two voltages; for example, an audio signal processing circuit,industrial measurement and control circuit, and so on.

In this manner, the present disclosure provides for improvements in thetechnical field of signal processing, as well as in the relatedtechnical fields of image sensing and image processing.

[Image Sensor]

FIG. 1 illustrates an exemplary image sensor 100 that implements modeswitching in a column sharing architecture, where each column of pixelcircuits shares a CDS circuit. Image sensor 100 includes an array 110 ofpixel circuits 111. The pixel circuits 111 will be described in moredetail below. The pixel circuits 111 are located at intersections wherehorizontal signal lines 112 and vertical signal lines 113 cross oneanother. The horizontal signal lines 112 are operatively connected to avertical driving circuit 120, also known as a “row scanning circuit,” ata point outside of the pixel array, and carry signals from the verticaldriving circuit 120 to a particular row of the pixel circuits 111. Thepixel circuits 111 in a particular column output an analog signalcorresponding to an amount of incident light to the vertical signal line113. For illustration purposes, only a small number of the pixelcircuits 111 are actually shown in FIG. 1; however, in practice theimage sensor 100 may have up to tens of millions of pixel circuits(“megapixels” or MP) or more.

The vertical signal line 113 conducts the analog signal for a particularcolumn to a column circuit 130. While FIG. 1 illustrates one verticalsignal line 113 for each column in the pixel array 110, the presentdisclosure is not so limited. For example, more than one vertical signalline 113 may be provided for each column, or each vertical signal line113 may correspond to more than on column. In any case, the columncircuit 130 preferably includes a plurality of CDS circuits 131.Individual CDS circuits 131 will be described in more detail below.Other possible circuit components of the column circuit 130, such as S/Hcircuits, voltage-to-current (V2I) circuits, counters, and the like, areomitted from the illustration of FIG. 1 for clarity purposes.

The column circuit 130 is controlled by a horizontal driving circuit140, also known as a “column scanning circuit.” Each of the verticaldriving circuit 120, the column circuit 130, and the horizontal drivingcircuit 140 receive one or more clock signals from a controller 150. Thecontroller 150 controls the timing and operation of various image sensorcomponents such that analog signals from the pixel array 110, havingbeen converted to digital signals in the column circuit 130, are outputvia an output circuit 160 for signal processing, storage, transmission,and the like.

During the readout process, the pixel circuits 111 in each row are readtogether, and the pixel circuits 111 in different rows are read in arow-by-row sequential basis. At the beginning of the processing period,a row of the pixel circuits 111 are connected to the CDS circuits 131via the vertical signal lines 113. The CDS circuits 131 sample andconvert a row of the pixel circuits 111 into digital form. After a rowof the pixel circuits 111 has been processed, the image sensor 100 turnsto the next row of the pixel circuits 111 and the process is repeated.This is continued until the entire frame is read out.

Two examples of pixel circuit 111 are pixel circuits 210 a and 210 b asillustrated in FIGS. 2A-B, which are pixel circuits of the so-called3T-type. As shown in FIG. 2A, pixel circuit 210 a includes aphotoelectric conversion device 201 a (for example, a photodiode), afloating diffusion FD, a reset transistor 202 a, a source followertransistor 203 a (sometimes called an “amplifier transistor”), aselection transistor 204 a, and a vertical signal line 205 a. Gateelectrodes of reset transistor 202 a and selection transistor 204 areceive signals RST and SEL, respectively. These signals may, forexample, be provided by the control or timing circuitry, such asvertical driving circuit 120 described above. Pixel circuit 210 a isoperated by first applying a value of the signal RST that causes thephotodiode 201 a to be cleared of charge and reset continuously. Whenthe signal RST is returned to ground, however, several effects may causethe value at a gate terminal of the source follower transistor 203 a tohave a value different from the reset voltage V_(rst). Major sources ofreset voltage level variations as measured by the vertical signal line205 a include variations from within the pixel 210 a and from outside ofthe pixel 210 a.

Variations from within the pixel 210 a include kTC noise, which iscaused by random variations in the channel resistance of the resettransistor 202 a combined with the capacitance at the gate terminal ofthe source follower transistor 203 a; reset charge injection, which iscaused by the high-low transition of the signal RST coupling through aparasitic capacitance C_(gs) between the gate and source terminals ofthe reset transistor 202 a; process variation of the transistors,including the threshold voltage V_(t) of the source follower transistor203 a and the drain-source voltage V_(ds) of the reset transistor 202 a;and additional parasitic capacitive coupling effects, such as thatbetween the RST signal line and the photodiode 201 a or metal wiringassociated with a sense node connected to source follower transistor204. Variations from outside the pixel 210 a include power and signaldistribution effects, such as IR drop associated with the pixel voltageand control signals across large arrays of pixels; and offsets andrandom noise occurring in the readout circuit which processes the outputof vertical signal line 205 a.

FIG. 2B illustrates another configuration of the 3T-type as pixelcircuit 210 b. In this circuit, the respective power supply voltages tothe source follower transistor 204 b and the reset transistor 203 b aredifferent. The select transistor 204 a of FIG. 2A is not used, whereas atransfer transistor 202 b is disposed between the photodiode 201 b andthe floating diffusion FD. In operation, the photodiode 201 b is resetby applying a high voltage at both the reset transistor 203 b and thetransfer transistor 202 b. Then the transfer transistor 202 b is turnedoff, and afterwards the floating diffusion FD is reset at which pointthe reset voltage is measured. After the pixel has been exposed tolight, the transfer transistor 202 b is turned on to move the chargefrom the photodiode 201 b to the floating diffusion FD. Then the resetplus light exposed value from the photodiode 201 b is measured.

While FIG. 2A-B illustrate pixel circuits having three transistors in aparticular configuration, the current disclosure is not so limited andmay apply to a pixel circuit having fewer or more transistors as well asother elements, such as capacitors, resistors, and the like.Additionally, the current disclosure may be extended to configurationswhere one or more transistors are shared among multiple photoelectricconversion devices.

Another example of pixel circuit 111 having a different number oftransistors is pixel circuit 310 as illustrated in FIG. 3. As shown inFIG. 3, pixel circuit 310 of the so-called 4T-type includes aphotoelectric conversion device 301 (for example, a photodiode), afloating diffusion FD, a transfer transistor 302, a reset transistor303, a source follower transistor 304 (sometimes called an “amplifiertransistor”), a selection transistor 305, and a vertical signal line306. Gate electrodes of transfer transistor 302, reset transistor 303,and selection transistor 305 receive signals TRG, RST, and SEL,respectively. These signals may, for example, be provided by the controlor timing circuitry, such as vertical driving circuit 120 describedabove.

In operation, floating diffusion FD is reset by asserting andde-asserting signal RST at the gate of reset transistor 303. Afterreset, a first measurement is done to capture a reset signal variationby asserting signal SEL and storing the reset signal variation outsideof the pixel. Next, signal TRG is asserted allowing the collected signalon the photodiode to be added to the reset signal. Then, a secondmeasurement is done to capture the reset plus photodiode signalvariation by asserting signal SEL. Finally, the previously-obtainedreset signal is subtracted from the second measurement using asubtraction method in analog or digital circuitry.

FIGS. 4A-B illustrate exemplary processing chains 400 a and 400 b toimplement subtraction methods in analog or digital circuitry,respectively. As illustrated in FIG. 4A, processing chain 400 a includesa pixel 410, which may be pixel 210 a/b, pixel 310, or another pixel; aswitch 420; an analog amplifier 430 configured to provide gain to theanalog signal; an analog CDS subtraction circuit 440 a configured toprovide a difference signal; and an ADC 450 configured to produce anoutput pixel value. Thus, CDS subtraction may be performed in the analogdomain.

As illustrated in FIG. 4B, processing chain 400 b includes a pixel 410,which may be pixel 210 a/b, pixel 310, or another pixel; a switch 420;an analog amplifier 430 configured to provide gain to the analog signal;an ADC 450 configured to convert from analog to digital values; and adigital CDS subtraction circuit 440 b configured to provide a differencesignal as an output signal. Thus, CDS subtraction may be performed inthe digital domain.

In practical circuit implementations, both processing chains 400 a and400 b may be controlled by a timing circuit, such as controller 150described above, and may be provided with memory and/or registers tostore any necessary intermediate values. Depending on the particularimplementation, the memory and/or registers may be provided for a singlepixel, a row of pixels, the entire image, and the like. In eitherimplementation, the pixel output undergoes an analog gain process priorto conversion to digital in ADC 450.

[Matched Comparator Active Reset Circuit]

FIG. 5 illustrates an exemplary matched comparator configurationincluding an active reset circuit 500 and a pixel circuit 510. Whilepixel circuit 510 is illustrated with its own matched comparator, otherconfigurations are possible. For example, there may be one active resetcircuit 500 per column, with each pixel circuit 510 in a given columnsharing the active reset circuit 500 for that column. Pixel circuit 510is illustrated as a 4T-type circuit, including a photodiode 501, atransfer transistor 502, a reset transistor 503, a source followertransistor 504, a selection transistor 505, and a holding capacitor 508.As illustrated, active reset circuit 500 shares source followertransistor 504 and selection transistor 505 with pixel circuit 510.Active reset circuit 500 additionally includes transistors 521-525provided separate from pixel circuit 510.

Transistor 522, source follower transistor 504, and selection transistor505 are disposed in a first current path between a power source voltageV_(dd2) and a column signal line 506. Transistors 523-525 are disposedin a second current path between power source voltage V_(dd2) and columnsignal line 506. In a case where, as noted above, multiple pixelcircuits 510 are connected or connectable to a single active resetcircuit 500, there may be multiple “first current paths” and one “secondcurrent path.”

As illustrated, the gates of transistors 522-523 are connected to oneanother, and transistor 523 is arranged in a diode configuration.Transistor 525 is controlled by an active reset signal RST2 at the gatethereof. The gate of transistor 524 receives an FD voltage resettingsignal RST3. Transistor 521 is disposed between a reset voltage V_(r)and the power supply line V_(dd). In operation, transistors 521 and 525are controlled so as to have opposite conductive states during operationof the associated image sensor. As illustrated, the active/passive resetselection is accomplished by making transistors 521 and 525 of anopposite channel time and providing the same control signal RST2 to bothsimultaneously. Therefore, when RST2 is high, transistor 521 is in anOFF state and transistor 525 is in an ON state, and when RST2 is low,transistor 521 is in an ON state and transistor 525 is in an OFF state.Alternatively, transistors 521 and 525 may be the same channel time, andinstead have opposite control signals supplied thereto.

Transistors 521 and 525 are used to control whether pixel circuit 510will perform a passive reset operation or an active reset operation.When RST2 is low, the pixel power source voltage V_(dd) is connected tothe reset voltage V_(r), while the second current path throughtransistors 523-525 is cut off by transistor 525. This allows for theperformance of the passive reset operation by controlling the resetsignal RST. When RST2 is high, on the other hand, the pixel power sourcevoltage V_(dd) is cut off from the reset voltage V_(r) by transistor521, and when selection signal SEL is also high the first current paththrough transistors 504-505 and 522, and the second current path throughtransistors 523-525 are both enabled to perform the active resetoperation, thus stabilizing the charge in the floating diffusioncapacitor and resulting in a reset voltage with smaller variation.

[Single-Slope ADC]

A single-slope ADC uses a ramp signal generated by a digital-to-analogconverter (DAC), and measures the analog signal from the sensor bycounting the time required by the ramp signal to cross the analog signalfrom the photodiode, thus providing a digital representation of theanalog signal. Single-slope ADCs, as with all other types of ADC, aresubject to circuit noise. In sensor operation, high levels of analoggain may be used to amplify the photodiode signal over the circuit noiselevel of the amplifier and ADC circuitry, thereby allowing the imagesensor to generate a useful image at low light levels and low readoutnoise. Thus, readout noise level is an important parameter for imagesensor implementations.

FIG. 6 illustrates an exemplary pixel circuit and single-slope ADC. Asillustrated in FIG. 6, a 4T pixel circuit 610 is connected to adifferential comparator 620 at one input thereof via signal line 606,and the other input of differential comparator 620 receives a rampsignal from a DAC 630. DAC 630 and pixel circuit 610 provide theirrespective signals to differential comparator 620 via a first couplingcapacitor 641 and a second coupling capacitor 642, respectively.

As illustrated, pixel circuit 610 includes a photodiode 601, a transfertransistor 602, a reset transistor 603, a source follower transistor604, a selection transistor 605, a current source 607, and a holdingcapacitor 608. Other pixel circuit designs, such as 3T or 5T+configurations, may be used in a similar arrangement. Differentialcomparator 620 includes transistors 621-629.

When the analog signal from pixel circuit 610 is sampled, DAC 630 isoperated to send out a ramp signal. FIG. 7A illustrates an exemplary setof signals, where the analog signal from pixel circuit 610 is shown as asolid line and the ramp signal generated by DAC 630 is shown as a dashedline. Because CDS is performed, the ramp signal is operated for twomeasurement periods. During the first measurement period, pixel circuit610 is reset. Just prior to the first measurement period, DAC 630 isreset to an initial level, and then the ramp signal ramps down under thecontrol of DAC 630. Digital comparator 620 changes state when the rampsignal crosses the pixel signal. Counting the time in DAC 630 for thisstate change to occur provides a measurement of the P-phase signal.

Thereafter, pixel circuit 610 is exposed to light, and DAC 630 isrestarted from the initial level before again ramping the ramp signaldown. Counting the time for this subsequent state change to occurprovides a measurement of the D-phase signal. The difference valuebetween the D-phase signal and the P-phase signal gives the output valueof pixel circuit 630.

To improve the accuracy of the measurements, an auto-zero (AZ) functionmay be performed. AZ is performed by turning on transistors 622 and 626,thus causing the two inputs of differential comparator 620 to becomeequal. As a result, capacitors 641 and 642 become charged so that any DCimbalance on the two sides of differential comparator 620 would causecapacitors 641 and 642 to charge to an appropriate level. The charge incapacitors 641 and 642 is maintained even when transistors 622 and 626are turned off. Therefore, the two inputs of differential comparator 620sense only the difference due to a change in the pixel signal or achange in the ramp signal.

The AZ process may be interpreted as one that stores the variations dueto circuit noise or other parameter differences in capacitors 641 and642. When the variation signals are stored and accounted for, the AZcircuit effectively performs measurement that is free from the noisecomponents such as thermal noise in the pixel circuit, pass-throughdispersion from the pixel circuit, offset error in the source followertransistor, non-zero offset in the two input terminals of thedifferential comparator, and the like. However, in a configuration wherethe image sensor utilizes a shared ADC structure where multiple columnsof pixels share a single ADC, the AZ method cannot remove the variationsresulting from the pixel readout in different columns. This is becausethe columns that share a single ADC must use a single AZ setting; thatis, a single stored value for the variations, even though each columnmay have different variations.

There may be additional sources of inaccuracies that the AZ circuit doesnot remove. For example, the signal line from pixel circuit 610 maydrift during the P-phase measurement by a non-zero amount ΔP, asillustrated in FIG. 7B. This drift may be due to factors such as thethermal noise in the AZ switches (transistors 622 and 626), switchingnoise due to non-zero on-impedance, parameter differences betweencomparators within the image sensor, different delays in the rampsignals, and the like.

[Active Reset with Single-Slope ADC]

To further improve the measurement accuracy, an active reset method fora single-slope ADC is preferably used. FIG. 8 illustrates an exemplaryactive reset circuit 800 using a 4T pixel circuit 810 and a single-slopeADC including a differential comparator 820 and a DAC 830. Asillustrated, pixel circuit 810 includes a photodiode 801, a transfertransistor 802, a reset transistor 803, a source follower transistor804, a selection transistor 805, a current source 807, and a holdingcapacitor 808 (sometimes called a “charge to voltage conversioncapacitor” or a “floating diffusion capacitor”). Pixel circuit 810 isconnected to differential comparator 820 via a signal line 806. Asabove, other pixel circuit designs, such as 3T or 5T+ configurations,may be used in a similar arrangement. Differential comparator 820includes transistors 821, 823-825, and 827-829. That is, as comparedwith differential comparator 620, two transistors as well as the twocapacitors have been omitted. Moreover, compared with FIG. 6, activereset circuit 800 has a connection from the comparator output line tothe source of reset transistor 803. Because no capacitor is presentbetween DAC 830 and the input of differential comparator 820, it may bepreferable to readjust the reset level of DAC 830 to match the DCoperating range of differential comparator 820.

To measure the pixel signal using active reset circuit 800, DAC 830 isinitialized to a reset level; for example, the initial level describedabove. Thereafter, reset signal RST is asserted to turn on resettransistor 803. At this point, a current flows from the output ofdifferential comparator 820 through reset transistor 803, thus chargingholding capacitor 808. This continues until holding capacitor 808 ischarged to a level that achieves a balanced state at differentialcomparator 820. When this occurs, differential comparator 820 hasachieved a neutral starting state which takes into account all of thenoise sources of the circuit, including differences in resistances andcapacitances of circuit elements, differences in parasitic resistancesand capacitances, offsets such as comparator offset, timing differences,and the like. In particular, two potentially-large noise sources, whichare the voltage variation in source follower transistor 804 and mismatchvariations in differential comparator 820, are removed. After this step,reset signal RST is de-asserted to turn off reset transistor 803, andthe circuit is now ready to perform measurements on the photodiodesignals.

Alternatively, a two-step reset transistor off control may be applied.FIG. 9 illustrates an exemplary waveform diagram for the two-step resettransistor off control. In this configuration, the steps of resettingDAC 830 and turning on reset transistor 803 are the same as describedabove. At this point, reset transistor 803 is in the ON state and thegate voltage of reset transistor 803 is at a high level, as shown in thefirst portion of FIG. 9. Subsequently, the gate voltage of resettransistor 803 is reduced from the high level to an intermediate level.This intermediate level is slightly below the gate voltage threshold ofreset transistor 803, such that reset transistor 803 is in a “weak ON”state. Finally, the gate voltage of reset transistor 803 is reduced to alow level. This low level is above the gate voltage threshold, such thatreset transistor 803 is in an OFF state. Because reset transistor 803 isstill conducting in the weak ON state, the more gradual method oftransitioning reset transistor 803 to the OFF state allows holdingcapacitor 808 to charge to a level that more accurately represents thevariations in the circuit elements. In other words, the two-step resettransistor off control reduces the through variation because it reducesthe swing of reset transistor 803.

After the two-step reset transistor off control is performed, theP-phase and D-phase signals from photodiode 801 may be measured in asimilar manner to that illustrated in FIG. 7A above; that is, bystarting a ramp signal from DAC 830 and measuring the time required forthe ramp signal to cross the pixel output signal. Because the noisevariations for each particular ADC circuit are stored in thecorresponding holding capacitor 808, a more accurate measurement of theP-phase and D-phase signals is obtained.

Active reset circuit 800 has a number of effects. For example, becauseactive reset is performed while connecting to a particular pixel circuit810, active reset circuit 800 is effective in a column sharing schemewhere multiple columns of pixels share a single ADC. In this case, thereset level of each column is stored in holding capacitor 803 asmeasurements are being taken, and thus overcomes the limitations of atraditional AZ method whereby only one set of noise variations may bestored for each ADC.

Additionally, active reset circuit 800 allows for a more efficient usageof silicon in the image sensor. Specifically, two transistors and twocapacitors are removed per ADC as compared to the circuit of FIG. 6. Inan image sensor implementation where thousands of ADCS are working inparallel, active reset circuit 800 results in a more efficient designwhich occupies a smaller area because of the reduced circuit elements.

Moreover, active reset circuit 800 controls the reset level of thefloating diffusion in pixel circuit 810 by feeding the output level ofdifferential comparator 820 and storing it in holding capacitor 803.This allows the reset level of the circuit to be controlled by adjustingthe reset level of DAC 830. In this manner, dark current in pixelcircuit 810 may be minimized by resetting pixel circuit 810 to thelowest voltage level necessary to support the used dynamic range at anygiven system gain; that is, at any analog gain of the circuit.

Furthermore, active reset circuit 800 allows the performance ofanalog-to-digital conversion on the analog pixel signals atsubstantially the same speed as a single-slope ADC that does notincorporate active reset, while still enabling full CDS and permittingthe use of high analog gain levels.

CONCLUSION

With regard to the processes, systems, methods, heuristics, etc.described herein, it should be understood that, although the steps ofsuch processes, etc. have been described as occurring according to acertain ordered sequence, such processes could be practiced with thedescribed steps performed in an order other than the order describedherein. It further should be understood that certain steps could beperformed simultaneously, that other steps could be added, or thatcertain steps described herein could be omitted. In other words, thedescriptions of processes herein are provided for the purpose ofillustrating certain embodiments, and should in no way be construed soas to limit the claims.

Accordingly, it is to be understood that the above description isintended to be illustrative and not restrictive. Many embodiments andapplications other than the examples provided would be apparent uponreading the above description. The scope should be determined, not withreference to the above description, but should instead be determinedwith reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled. It is anticipated andintended that future developments will occur in the technologiesdiscussed herein, and that the disclosed systems and methods will beincorporated into such future embodiments. In sum, it should beunderstood that the application is capable of modification andvariation.

All terms used in the claims are intended to be given their broadestreasonable constructions and their ordinary meanings as understood bythose knowledgeable in the technologies described herein unless anexplicit indication to the contrary in made herein. In particular, useof the singular articles such as “a,” “the,” “said,” etc. should be readto recite one or more of the indicated elements unless a claim recitesan explicit limitation to the contrary.

The Abstract of the Disclosure is provided to allow the reader toquickly ascertain the nature of the technical disclosure. It issubmitted with the understanding that it will not be used to interpretor limit the scope or meaning of the claims. In addition, in theforegoing Detailed Description, it can be seen that various features aregrouped together in various embodiments for the purpose of streamliningthe disclosure. This method of disclosure is not to be interpreted asreflecting an intention that the claimed embodiments require morefeatures than are expressly recited in each claim. Rather, as thefollowing claims reflect, inventive subject matter lies in less than allfeatures of a single disclosed embodiment. Thus the following claims arehereby incorporated into the Detailed Description, with each claimstanding on its own as a separately claimed subject matter.

What is claimed is:
 1. An image sensor, comprising: a pixel circuitincluding a reset transistor and an amplification transistor, the pixelcircuit configured to output a pixel signal; an amplifier including apixel input and an amplifier output; a capacitor connected to one of asource or a drain of the reset transistor and to the amplificationtransistor; a first signal line connected to the pixel circuit and tothe amplifier; and a second signal line connected to the other of thesource or the drain of the reset transistor and to the amplifier output.2. The image sensor according to claim 1, wherein the capacitor isconnected to a gate of the amplification transistor.
 3. The image sensoraccording to claim 2, wherein the amplifier is configured to receive thepixel signal at the pixel input and to receive a reference signal at areference input.
 4. The image sensor according to claim 1, furthercomprising a correlated double sampling (CDS) circuit, wherein: the CDScircuit is configured to perform a P-phase measurement corresponding toa reset level of the pixel circuit, and the CDS circuit is configured tosubsequently perform a D-phase measurement corresponding to a data levelof the pixel circuit.
 5. The image sensor according to claim 4, whereinthe CDS circuit is configured to calculate a difference between theP-phase measurement and the D-phase measurement.
 6. The image sensoraccording to claim 1, wherein a gate of the reset transistor isconfigured to receive a high reset level, an intermediate reset level,and a low reset level in this order.
 7. The image sensor according toclaim 6, wherein the high reset level and the intermediate reset levelare higher than a gate threshold of the reset transistor, and the lowreset level is lower than the gate threshold of the reset transistor. 8.The image sensor according to claim 1, wherein the pixel circuit furtherincludes a photodiode and a transfer transistor.
 9. The image sensoraccording to claim 8, wherein the pixel circuit further includes aselection transistor.
 10. The image sensor according to claim 1, whereinthe pixel circuit is one of a plurality of pixel circuits arranged in amatrix, and the amplifier corresponds to a plurality of columns of thematrix.
 11. An image processing method, comprising: outputting a pixelsignal via a first signal line from a pixel circuit, the pixel circuitincluding a reset transistor, an amplification transistor, and acapacitor connected to one of a source or a drain of the resettransistor and to the amplification transistor; and outputting anamplifier signal via a second signal line from an amplifier, theamplifier including a pixel input and an amplifier output, wherein thesecond signal line is connected to the other of the source or the drainof the reset transistor.
 12. The image processing method according toclaim 11, wherein the capacitor is connected to a gate of theamplification transistor.
 13. The image processing method according toclaim 12, further comprising receiving the pixel signal at the pixelinput and to receiving a reference signal at a reference input of theamplifier.
 14. The image processing method according to claim 11,further comprising: performing a P-phase measurement corresponding to areset level of the pixel circuit; and thereafter performing a D-phasemeasurement corresponding to a data level of the pixel circuit.
 15. Theimage processing method according to claim 14, further comprisingcalculating a difference between the P-phase measurement and the D-phasemeasurement.
 16. The image processing method according to claim 11,further comprising: receiving, at a gate of the reset transistor, a highreset level, an intermediate reset level, and a low reset level in thisorder.
 17. The image processing method according to claim 16, whereinthe high reset level and the intermediate reset level are higher than agate threshold of the reset transistor, and the low reset level is lowerthan the gate threshold of the reset transistor.
 18. The imageprocessing method according to claim 11, wherein the pixel circuitfurther includes a photodiode and a transfer transistor.
 19. The imageprocessing method according to claim 18, wherein the pixel circuitfurther includes a selection transistor.
 20. The image processing methodaccording to claim 11, wherein the pixel circuit is one of a pluralityof pixel circuits arranged in a matrix, and the amplifier corresponds toa plurality of columns of the matrix.